1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a multiplier oscillator that multiplies a clock signal.
2. Description of Related Art
A ring oscillator is generally known as a circuit that generates an internal clock signal with a high frequency (see Japanese Patent Application Laid-open No. 2010-192976). The ring oscillator includes odd numbers of inverter circuits cyclically-connected to generate a clock signal with a predetermined frequency depending on not only the number of stages of the inverter circuits, but also characteristics of transistors included in the inverter circuits, an operating voltage, and the like. The clock signal generated by the ring oscillator is supplied to, for example, a PLL (Phase-Locked Loop) circuit, so that an internal clock signal having higher frequency than that of an external clock signal supplied from outside can be obtained.
However, in the PLL circuit using the ring oscillator, a generable frequency of the internal clock signal is limited by the oscillation frequency of the ring oscillator and thus the oscillation frequency of the ring oscillator needs to be increased to generate the internal clock signal with a higher frequency. Accordingly, in some cases, a boosted potential needs to be used as the operating voltage of the ring oscillator, which increases the circuit scale.
In recent years, the operating voltage of a semiconductor device tends to be lowered from a viewpoint of reducing power consumption or decreasing jitter. Meanwhile, a threshold voltage of a transistor is sometimes designed to be sufficiently high to reduce an off-leakage current of the transistor. A decrease in the operating voltage or an increase in the transistor threshold voltage increases a delay amount of each stage of the inverter circuits included in the ring oscillator, which increases difficulty in increasing the oscillating frequency of the ring oscillator.
In the PLL circuit using the ring oscillator, when there is a slightest difference between the frequency of the external clock signal and the oscillating frequency of the ring oscillator, the difference is accumulated little by little and consequently a large phase difference may be caused. To reduce such a phase difference, a correction operation for the oscillating frequency needs to be constantly performed, which increases the power consumption.
With this background, a semiconductor device including a multiplier oscillator that can generate an internal clock signal with a high frequency without using a ring oscillator has been demanded.